As power densities in integrated circuits (ICs) increases with faster clock frequencies and smaller die size, controlling circuit temperatures has become an important aspect of IC design. With increasing temperatures, the sub-threshold leakage power, interconnect delay and crosstalk noise also increase. Furthermore, high temperature operation reduces the lifetime of an IC, and increases the cost of an IC's thermal package. Consequently, efficient thermal design is becoming increasingly important to IC design.
The thermal properties of a proposed IC design may be evaluated by computationally predicting the temperature distribution of the active elements during operation. The temperature distribution allows one to determine the maximum temperatures the chip will endure, and allows designers to exclude designs that exceed the critical junction temperature. This thermal analysis is complicated by the spatial and temporal non-uniform heating found in contemporary microprocessors, resulting in certain regions, known as “hot spots,” exceeding the mean operating temperature. Therefore, to identify the extreme temperatures produced by hot spots, it is desirable to calculate a full temperature map of the IC's surface under steady state and transient conditions. The traditional approach in order to calculate the temperature distribution in a given solid involves solving the heat equation with the appropriate boundary conditions. The most common techniques for solving a generic PDE are finite differences and finite elements, which are usually performed in the time or in the frequency domain. However, their accuracy comes at the price of long execution times, and exhaustive CPU and memory usage. From a specified power map of a proposed IC design, current methods, such as finite element analysis (FEA), calculate the resulting temperature distribution using the differential heat conduction equation,
                                          ρ            ⁡                          (                              x                →                            )                                ⁢                      c            ⁡                          (                              x                →                            )                                ⁢                                    ∂                              T                ⁡                                  (                                                            x                      →                                        ,                    t                                    )                                                                    ∂              t                                      =                              H            ⁡                          (                                                x                  →                                ,                t                            )                                +                                    ∇                              x                →                                      ⁢                          ·                              (                                                      λ                    ⁡                                          (                                              x                        →                                            )                                                        ⁢                                                            ∇                                              x                        →                                                              ⁢                                          T                      ⁡                                              (                                                                              x                            →                                                    ,                          t                                                )                                                                                            )                                                                        Eq        .                                  ⁢        1            where, T, H, ρ, c, and λ denote temperature, heat flux, mass density, specific heat and thermal conductivity, respectively. While this method is accurate, it is computationally very time consuming. Consequently, it is not practical for use with a very large number of nodes in a chip, or for use with routing and placement optimization algorithms.
One proposed method is to model an IC as a thermal resistor and capacitor network. This method has been used to accurately predict steady temperature distributions in very large scale integration (VLSI) systems in order to reduce hot spot temperatures. However, this method is limited by the considerable effort necessary to model each sub-region of an IC's surface as a circuit consisting of connections through the package to the heat sink, where each layer's resistance must be found analytically or experimentally. A further limitation of this method is the substantial calculation times associated with solving a complex network and, consequently, its incompatibility with routing and placement optimization algorithms.
Consequently, a faster method to ensure proper thermal design would be a desirable advance in the field of IC chip design. Fast thermal simulations have been explored using a Green's function technique where analytical expansions of the Green's function are used. See, for example, Cheng et al., “An Efficient Method for Hot-spot Identification in ULSI Circuits,” Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design 1999. Pages: 124-127.; Zhan et al., “A High Efficiency Full-Chip Thermal Simulation Algorithm,” IEEE, pp. 634-637, 2005; and Zhan et al., “Fast Computation of the Temperature Distribution in VLSI chips using the Discrete Cosine Transform and Table Look-up,” Proc. 2005 Asia and South Pacific Design Automation Conference, pp. 87-92, January 2005. However, because accurate analytical solutions exist only for very simple geometries, it is extremely difficult to obtain analytical solutions with realistic IC design packages having high complexity. As a result, these approaches are of limited use.